From hardware design intent to verifiable KiCad schematics, durable project state, reviewable placement, and reconciled manufacturing outputs.
Describe the design, validate it through a real intermediate model, and generate an inspectable artifact bundle. Every path follows the same contract: describe → validate → generate — with explicit proof when KiCad verification ran.
Each step shows what runs (the engine, script, or slash command), what happens, and what it produces.
Engineer + Codex / Claude define block intent, interfaces, power rails, buses, and constraints — no hand-drawing every schematic page first.
Distributor workflow skills resolve vague component choices into concrete MPNs, datasheets, and pricing. KiCad symbols are pulled directly from DigiKey and JLCPCB — no manual library management.
Assembles part bindings, block topology, support-circuit requirements, and all overrides into a single machine-readable YAML design IR.
Emits .kicad_sch files, placement hints, review SVGs, and design reports. Auto-generates bypass caps, support passives, and topology motifs from the YAML spec. Runs a 14-point validation pipeline.
Generated schematics are typically ~90% complete for serious hardware work. The last editorial pass — page aesthetics, label readability — is done in KiCad.
Pull the schematic into KiCad PCB, place parts with the simulated-annealing optimizer, route critical nets manually. Use autoroute / Freerouting for non-critical nets where it actually helps.
Review artifacts, verification evidence, and manufacturing files reconciled against the authoritative electrical PCB.
Every default circuit-weaver generate run emits an inspectable, manifest-driven artifact bundle — not just a schematic.
Real, loadable root schematic plus collision-safe functional sub-sheets, with verification state recorded against the exact final file.
Validation results, per-IC component selection rationale, DFM score, and BOM — rendered in a self-contained HTML file for design review.
Auto-detected power, ground, clock, bus, and differential-pair nets — annotated on the schematic and exported as a CSV for bring-up probing.
BOM and CPL delivery reconciled against real electrical-PCB references and footprints, with delivery_manifest.json as the commit marker.
MCU pin map CSV, STM32 .ioc skeleton, and ESP32 sdkconfig.defaults — generated automatically for every MCU block in the design.
Parametric OpenSCAD enclosure automatically sized to the PCB outline — ready to render to STL and 3D-print.
Editable, blocker-aware review proposal with exhaustive assembly reconciliation. It remains explicitly non-fabrication data until applied to the real electrical PCB.
The electrical PCB is created by KiCad from the generated schematic, preserving the authoritative pads and nets required for routing, DFM, and Gerber export.
Design log traces every research decision, IC selection rationale, and spec mutation — persisted across sessions for a full audit trail.
Portable relative paths, file kinds, sizes, verification state, and the canonical root schematic — downstream tools consume the manifest instead of guessing filenames.
Atomic state, fingerprinted imports, cached analysis, and deterministic restart plans for KiCad projects, PCBs, Gerbers, drill sets, and ZIP archives.
Topology, connections, hierarchy coherence
Power, ground, net integrity, ERC pass
Part bindings, footprint assignments, MPNs
Labels, pin numbers, net names, readability
Hotspot proximity, power dissipation clustering, thermal constraint violations
Timing checks, differential-pair balance, signal quality across critical nets
Rail isolation, domain boundary coherence, pin coverage across power network
Most automation tools stop at "did the output file exist." Circuit Weaver runs a 14-point validation pipeline covering electrical safety, thermal constraints, signal integrity, and power domains — so the schematic is structurally sound and review-ready before you ever open KiCad.
Failures are grouped and labeled. You know exactly what category failed and why, not just that something went wrong in the hardware design workflow.
A complete electronic design automation surface, not a collection of one-off scripts.
Emits real .kicad_sch files from a canonical YAML spec. Auto-adds bypass caps, support passives, and topology motifs. Outputs review-ready SVGs and design reports.
14-point pipeline covering electrical safety, thermal constraints, signal integrity, power domains, and pin coverage. The output must be loadable, coherent, sourced, and reviewable — not just "did the export finish."
Apply design mutations atomically — reject on failure, never silently corrupt the spec. Diff two canonical designs semantically. Ingest PCB feedback as constraints back into the spec.
KiCad symbols pulled directly from DigiKey and JLCPCB — no manual library hunting. Mouser, LCSC, and PCBWay workflow skills resolve the rest: MPNs, package decisions, datasheets, and pricing.
A full FastAPI server wraps every engine capability over HTTP. Generate schematics from YAML, validate specs, apply patches, and diff designs — all accessible over REST.
Designed as a machine-readable contract. Codex, Claude, and any LLM-based agent can validate, patch, diff, and generate through the Python API or HTTP endpoints predictably.
Simulated annealing optimizer with --strategy thermal minimizes overlap, thermal clustering, and DFM zone penalties. Interactive HTML viewer with thermal heatmap overlay and net highlight. Inkscape SVG round-trip: export → edit → import back into KiCad PCB.
Auto-generates {project}_pinout.csv, a STM32 .ioc skeleton, and ESP32 sdkconfig.defaults for every MCU block — keeping firmware pin assignment in sync with the schematic without manual hand-off.
Runs inside every generate_artifacts() call — classifies power, ground, clock, bus, and differential-pair nets, annotates the schematic with TP labels, and emits {project}_test_points.csv for bring-up and debug.
ngspice integration runs circuit simulation directly from the YAML spec — verify operating points, transient response, and AC characteristics before committing to layout.
Identifies and visualizes thermal hotspots across the board. Power dissipation per component feeds directly into the placement optimizer's thermal-aware strategy.
Timing and signal quality checks across critical nets. Differential-pair balance, net length constraints, and crosstalk flags surface before schematic sign-off.
0–100 design readiness score synthesized from validation results, resolver coverage, simulation outcomes, and DFM checks — one number that summarizes design state.
Nine complete reference designs — YAML spec to validated KiCad schematic, BOM, and placement files. Click any card to explore.
From topology-aware zone layout to panelization — a six-step pipeline for going from schematic to manufacturable PCB placement.
Topology-aware zone layout: power zone, digital zone, RF zone, connector zone, and passive banks — emits placement.svg and design.kicad_pcb.
$ circuit-weaver generate design.yaml -o ./outputMinimizes overlap, boundary violations, thermal clustering, and DFM zone penalties. Thermal-aware strategy reduces hotspot proximity.
$ circuit-weaver optimize-placement design.yaml --strategy thermal --iterations 10000Click-to-highlight nets, component hover tooltips (value, footprint, MPN), thermal heatmap overlay (blue→red by power dissipation), CSV export.
$ circuit-weaver placement-viewer design.yaml -o output/viewer.htmlEdit component positions in Inkscape using the exported SVG, then import edits directly back into the KiCad PCB file.
$ circuit-weaver import-placement placement.svg board.kicad_pcb board_updated.kicad_pcbWhen a compatible KiCad Python API is installed, apply reviewed coordinates to the real electrical PCB without an SVG round-trip.
from circuit_weaver import (
check_kicad_available,
update_board_placements,
)Run DFM rules against JLCPCB constraints, then panelize for multi-up fabrication and export dual CPL files.
$ circuit-weaver check-dfm design.yaml
$ circuit-weaver panelize design.yaml
$ circuit-weaver export-dual-cpl design.yamlEvery engine capability is exposed over HTTP so you can run it locally or deploy it as a circuit design API.
The integrity and compatibility release: exact-file KiCad verification, durable import and resume, professional hierarchy, blocker-aware placement review, reconciled manufacturing export, and aligned agent workflows — available now via pip install circuit-weaver.
Deterministic sheet and reference allocation, collision-safe symbol naming, strict rendered pin maps, final S-expression checks, and safer wire and label movement for dense designs.
ERC runs against the exact final schematic. Results expose kicad_verified and verification_status, while --require-kicad fails closed when verification cannot run.
Atomic project state plus non-destructive KiCad, PCB, Gerber, drill, and ZIP import. Fingerprinted analysis is cached, while status and resume return a deterministic restart plan.
Explicit block sections remain separate functional sheets, support parts retain ownership, and collision-safe filenames preserve readable hierarchy instead of flattening a professional design.
Placement JSON, context, SVG, and HTML reconcile the exact assembly inventory and surface overlap, boundary, geometry, sourcing, and constraint blockers with official-reference links.
JLCPCB and CPL export reconcile real PCB references and footprints. Freerouting publishes validated SES sessions and reports incomplete routing as partial instead of claiming completion.
Portable kebab-case skills, narrower triggers, provenance-aware upgrades, and aligned install paths now serve Codex, Claude Code, and OpenCode from one package.
Legacy imports and deprecated aliases are restored, YAML parsing is strict, placement SVGs carry real data, and the artifact manifest inventories every output with portable paths.
Python 3.10–3.14, blocking Windows coverage, exact-wheel tests, live MCP tests, and KiCad 8, 9, and 10 generation and ERC gates now run before PyPI publication.
Quality-gated samples target zero wire-through-body crossings through body-aware stubs, tapped-rail splitting, precise keep-outs, and shared layout-quality analysis.
Connector-heavy layouts use a continuous density score, while designs that exceed A0 split into readable area-balanced functional sheets instead of shipping a crammed page.
Normalized pin roles now flow through component definitions, IC data, EasyEDA imports, generic builders, and cache round-trips, enabling vendor-neutral interface repair.
Freerouting preflight rejects preview, pad-less, and net-less boards; effort and timeout controls are explicit, and incomplete-route counts remain visible in every result.
# Install # pip install circuit-weaver from circuit_weaver.dispatcher import ( validate_design, apply_design_patch, generate_artifacts, diff_designs, ingest_pcb_feedback, ) # Load your canonical spec spec = yaml.safe_load(open("design.yaml")) # Validate (14-point pipeline) report = validate_design(spec) # Apply a transactional patch result = apply_design_patch(spec, patch) # Generate the full KiCad bundle bundle = generate_artifacts( spec, output_dir="out/design", profile="mvp_strict", )
Install the package, point it at a YAML spec, and generate real KiCad schematics without building bespoke hardware automation scripts.
14-point validation pipeline — returns a structured report covering electrical safety, thermal, signal integrity, power domains, and pin coverage
Atomic in-memory mutation — reject on failure, never silently corrupt the design state
Emits the full KiCad bundle: .kicad_sch files, placement hints, review SVGs, and a design report
Semantic change report — understand exactly what changed between two design revisions
Feed PCB layout feedback back into the canonical design spec as layout constraints
Every command, organized by workflow stage. Run circuit-weaver --help or circuit-weaver <subcommand> --help for full flag reference.
$ circuit-weaver validate design.yaml
$ circuit-weaver generate design.yaml -o ./output
$ circuit-weaver erc output/design.kicad_sch
$ circuit-weaver diff old.yaml new.yaml$ circuit-weaver optimize-placement design.yaml --iterations 5000 --seed 42
$ circuit-weaver placement-viewer design.yaml -o output/viewer.html
$ circuit-weaver import-placement placement.svg board.kicad_pcb out.kicad_pcb
$ circuit-weaver check-dfm design.yaml
$ circuit-weaver panelize design.yaml
$ circuit-weaver export-dual-cpl design.yaml$ circuit-weaver cost-bom design.yaml --qty 1,10,100
$ circuit-weaver export-jlcpcb design.yaml -o ./jlcpcb
$ circuit-weaver export-gerbers design.yaml -o ./gerbers$ circuit-weaver simulate design.yaml
$ circuit-weaver confidence design.yaml
$ circuit-weaver design-enclosure --board-width 50 --board-height 40
$ circuit-weaver harvest-specs design.yaml
$ circuit-weaver fetch-spice design.yamlCircuit Weaver ships as a global skill for Claude Code, Codex, and OpenCode — one install command wires it up to your agent workflow.
Global /circuit-weaver skill installed via install-skills. Run directly in Claude Code terminal sessions — validates, patches, and generates without leaving your editor.
/circuit-weaver
Portable global skill installed with provenance-aware upgrade safety. Launch the complete design workflow directly from a Codex task.
$circuit-weaver
Installed through the portable skills path and loaded through OpenCode's native skill tool, with the same describe → validate → generate contract.
.agents/skills/circuit-weaver
# Install the package
pip install circuit-weaver
# Register skills for all platforms
circuit-weaver install-skills
# Launch in Claude Code or Codex
/circuit-weaver # Claude Code
$circuit-weaver # Codex
# Or run fully offline
circuit-weaver design-wizardHonest answers about Circuit Weaver — capabilities, differentiators, and current limits.
Circuit Weaver is a spec-first, AI-assisted circuit design system. Describe the design, validate it through a real intermediate model (DesignIR), and generate real KiCad schematics — not stubs, not templates, not chat artifacts. The same engine serves every entry point: Claude Code skill, Codex agent, CLI wizard, HTTP API, or direct Python import.
Three things. First, a real intermediate model — DesignIR is a typed, structured representation that every tool reads from, not a string buffer of chat prompts. Second, a layered architecture — skills and docs on top, deterministic Python validation/compilation/generation beneath, communicating through the IR not through prompt engineering. Third, auditable provenance — every IC choice, research citation, and session decision is logged to .design_log.json so design rationale survives the chat session that produced it.
Speed to structure. Turning a fuzzy embedded-board idea into a structured, reviewable artifact set — fast — is where we win. Validation that means something. Placement-readiness is hard-gated, not a cosmetic warning bucket. Full lifecycle coverage. Requirements → IC selection → schematic → confidence scoring → placement prep → manufacturing export — most tools stop at one stage. Reusable core. Same engine serves CLI, agents, API, and imports. No per-platform fork.
Best on standard embedded boards. Weaker on odd parts, custom pinouts, exotic buses, RF, and unusual power trees. Part metadata is everything. If IC data, pin maps, or footprint bindings are weak, the experience degrades fast. Validation edge cases remain. False positives still exist in some corners. Workflow can drift from engine. Skills, docs, and runtime constraints need active synchronization. PCB closure is not push-button. Final routing, layout judgment, and fab signoff remain manual — we accelerate the front 80%, not the last mile.
Yes. Circuit Weaver generates real .kicad_sch files, review artifacts, and validation reports — the output moves into actual engineering review and PCB implementation, not a dead-end diagram.
Yes. The simulated annealing optimizer runs with circuit-weaver optimize-placement, supports thermal-aware strategy, and produces topology-aware zone placement (power, digital, RF, connector, passive banks). An interactive HTML viewer shows a thermal heatmap and net highlights. Placements export as SVG, round-trip through Inkscape, and import back into KiCad.
Firmware co-design stubs: {project}_pinout.csv, STM32 .ioc skeleton, and ESP32 sdkconfig.defaults. Auto test points: power, ground, clock, bus, and differential-pair nets get annotated TP labels and a {project}_test_points.csv. Manufacturing: BOM and CPL export for JLCPCB and PCBWay, with LCSC part matching, price-break detection, and assembly variant support.